階層化不完全LU法及其在準靜態金氧半場效電晶體電容模擬上的應用

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姓名

孫郁明(Yu-Ming Sun ) 查詢紙本館藏

畢業系所

電機工程研究所

論文名稱

階層化不完全LU法及其在準靜態金氧半場效電晶體電容模擬上的應用
(Levelized Incomplete LU Factorization and Its Application to Quasi-Static MOSFET C-V Simulation)

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摘要(中)

本論文著重在以二維等效電路模型利用階層化不完全LU分解法進行準靜態金氧半場效電晶體電容的模擬分析。在二維的元件模擬中，傳統的LU分解法產生大量的非零項，消耗大量的記憶體空間，二維的元件模擬往往無法在個人電腦上進行，階層化不完全LU分解法解決此一問題。在模擬的過程中，採用金屬閘極的結構和交錯式的變數排列方法，這是因為金屬閘極的結構較多晶矽閘極結構節省許多格子點，交錯式的變數排列方式更有效降低非零項的產生。本論文使用電荷法(charge method)，弦波法(sinusoidal method)，斜波法(ramp method)三種方法模擬量測準靜態金氧半場效電晶體閘極-基極電容、閘極-源極電容、閘極-吸極電容，並分析比較模擬結果。最後，我們也嘗試改變資料儲存的型態以節省記憶體空間，然而效果非常有限，因而建議一種個別求解的方式(decoupled method)以減少非零項的產生，有效利用記憶體空間。

摘要(英)

In this thesis, we focus our attention on the measurement of the quasi-static MOSFET capacitance and Levelized incomplete LU method. Direct LU decomposition is not suitable for large-scale device simulation, because a lot of fill-ins will be generated during LU decomposition. Levelized incomplete LU method provides a good way to improve traditional LU decomposition. The structure of the metal gate and the method of the interleaving variable permutation are used. The use of the metal gate can save some rectangular grids which are used to describe the poly gate terminal. The use of the interleaving method reduces the number of fill-ins. In the meantime, the main focus of this thesis is on the measurement of gate to substrate, gate to source, and gate to drain capacitances of MOSFET. These measurements are implemented by charge method, sinusoidal method, and ramp method. The results of C-V characteristics are compared. Finally, we try to reduce memory space by changing the data type, but it is quite difficult. Therefore, we proposed decoupled method to reduce the number of nonzero entries.

關鍵字(中)

★ 階層化不完全LU分解法

關鍵字(英)

★ LILU

論文目次

Contents
1.Introduction 　
2.Two-dimensional Semiconductor Device Simulation
Using LILU
2.1 2D Equivalent Circuit Model
2.2 Levelized Incomplete LU Method
2.3 Sequential and Interleaving Methods for Variable
2.4 Metal Gate and Poly Gate
3.Measurement of Quasi-Static MOSFET
Capacitance
3.1 Quasi-Static MOSFET Capacitances
3.2 A Charge Method for MOSFET Capacitances 　
3.3 A Sinusoidal Method for Measuring MOSFET Capacitances 　
3.4 A Ramp Method for Measuring Quasi-Static MOSFET Capacitances
4.Investigation on Memory Reduction
4.1 Data Structure Methods for Reducing Memory Space
4.2 Decoupled Method
5. Conclusion

參考文獻

Reference
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[2]M. K. Tsai, "An Improve Levelized Incomplete LU Method and Its Application to 2D Semiconductor Devices Simulation," M. S. thesis, National Central University, Taiwan, Republic of China, 2000.
[3]H. D. Casey jr, Devices for Integrated Circuits, Silicon and Ⅲ-ⅤCompound Semiconductors, John Wiley & Sons, Inc.
[4]K. M. Rho, K. Lee, M. Shur, and T. A. Fjeldly, "Unified Quasi-Static MOSFET Capacitance Model," IEEE Transactions on Electron Device, vol. 40, pp. 131-136, Jan. 1993.
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[7]D. H. Cho, S. M. Kang, K. H. Kim, and S. H. Lee, "An Accurate Intrinsic Capacitance Modeling for Deep Submicrometer MOSFET's," IEEE Transactions on Electron Devices, vol. 42, pp 540-548, Mar. 1995.
[8]D. Flandre, F. V. D. Wiele, P. G. A. Jespers, and M. Haond, "Measurement of Intrinsic Gate Capacitances of SOI MOSFET's," IEEE Electron Device Letters, vol. 11, pp. 291-293, Jul. 1990.
[9]H. J. Park, P. K. Ko, and C. Hu, "A Non-Quasi-Static MOSFET Model for SPICE-AC Analysis," IEEE Transactions on Computer-Aided Design, vol. 11, pp. 1247-1257, Oct. 1992.
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[11]Y. T. Tsai and L. C. Huang, "Simulation of Amorphous Silicon Thin-film Transistor Including Adapted Gummel Method," International Journal of Numerical Modeling Electronic Networks, Devices And Fields, vol. 10, pp. 3-11, 1997.

指導教授

蔡曜聰(Yao-Tsung Tsai)

審核日期

2001-7-5

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